Designing integrated circuits (ICs) with tens of thousands or even millions of transistors is known as VLSI (Very Large Scale Integration), and it is a challenging procedure. The VLSI design flow Chart is shown below
The process of VLSI implementation is as shown
Physical verification technique: DRC- Design rule check, LVS- Layout versus schematic, ERC –Electrical rule check These techniques are mandatory to check a design and its structure before manufacturing.
VLSI Software tools There are a variety of software tools that may be used by designers to generate and test their IC designs to help with the design process. Several well-known VLSI design software applications are: Cadence Virtuoso • A highly common software application for creating and simulating analogue and digital circuits • It offers a complete platform for simulation, layout design, and schematic capture.
Synopsys • A set of software tools for designing and testing IC designs, such as design compilers, simulators, and verification tools.
Mentor Graphics • A software program that offers a full-featured environment for creating, simulating, and checking IC designs. • It provides tools for layout design, simulation, and schematic capture.
Xilinx ISE • A programme for creating and evaluating field-programmable gate arrays (FPGAs). • For creating, simulating, and verifying FPGA designs, it comes with an entire suite of design tools.
Tanner EDA • A software tool that offers a full design and simulation environment for mixed-signal and analogue circuits. • A schematic capture tool, a layout editor, and a simulation tool are all included.
List the coding language used in IC Design coding • System Level Design (algorithmic level): C, MATLAB, SystemC • RTL Level Design: Verilog HDL,VHDL • Gate Level Design(Post-Synthesis): Verilog HDL , VHDL • Transistor Level Design: SPICE • Simulation and Verification of Design: Verilog HDL , VHDL , System Verilog(OOPs) • Scripting: Perl, TCL. List the CAD Tools in IC Design • Simulation Tools(HDL): Synopsys (VCS), Cadence (NCSIM), Mentor(ModelSim) • Synthesis: Synopsys (Design Vision), Cadence (RTL Compiler/Genus) • PNR Tools: Synopsys (IC Compiler), Cadence (SoC Encounter/Innovus) • Spice Simulation Tool: Cadence SPECTRE, Synospys HSPICE, Mentor(Eldo Spice • DRC, LVS Tools: Cadence (Assura), Mentor(Calibre),Synopsys(Hercules) • Verification Tools: Synospys (VCS),Cadence (NCSIM), Mentor • (Questa Sim / ModelSim) • Formal Verification: Synopsys(Formality/VC-Formal),Cadence(JasperGold) • Timing Analysis: Synopsys(Primetime), Cadence(EDI/Tempus) • Testing: Synopsys(DFT Compiler, TetraMax), Cadence (Modus)
VLSI design flow from the point of CAD is shown below.
