- What is latch up?
Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS)
- Why is NAND gate preferred over NOR gate for fabrication?
NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it is more symmetric in case of NAND (the delay profile), but for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher resistance p mos’s are in series connection which again increases the resistance).
- What is Noise Margin? Explain the procedure to determine Noise Margin
The minimum amount of noise that can be allowed on the input stage for which the output will not be effected.
- Explain sizing of the inverter?
In order to drive the desired load capacitance we have to increase the size (width) of the inverters to get an optimized performance.
- What are the limitations in increasing the power supply to reduce delay?
The delay can be reduced by increasing the power supply but if we do so the heating effect comes because of excessive power, to compensate this we have to increase the die size which is not practical.